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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Register Map and Description
The device contains a bank of volatile registers that
store its settings and status. The device features an I 2 C-
compatible, 3-wire serial interface, allowing the registers
to be fully software configurable and programmable. In
addition, several registers are also pin-programmable
to allow the device to operate in auto mode and still
be partially configurable even without the assistance of
software.
Interrupt Registers (R00h, R01h)
Interrupt Register (R00h)
The Interrupt register (R00h, Table 6) summarizes the
Event Register status and is used to send an interrupt
Table 6. Interrupt Register
signal to the controller. On power-up or after a reset
condition, interrupt (R00h) is set to a default value of 00h
(it may almost immediately report an interrupt depend-
ing on if it was a power-up or reset condition, and in the
case of reset the type/cause of reset). INT goes low to
report an interrupt event if any one of the active interrupt
bits is set to 1 (active-high) and it is not masked by the
Interrupt Mask register (R01h, Table 7). INT does not go
low to report an interrupt if the corresponding mask bit
(R01h) is set. Writing a 1 to INT_CLR (R1Ah[7], Table 27)
clears all interrupt and events registers (resets to low).
INT_EN (R17h[7], Table 24) is a global interrupt enable
and writing a 0 to INT_EN disables the INT output, put-
ting it into a state of high impedance.
ADDRESS = 00h
SYMBOL BIT NO.
TYPE
DESCRIPTION
SUP_INT
TST_INT
7
6
R
R
Interrupt signal for supply faults. SUP_INT is the logic OR of all the active bits in the Supply
Event register (R0Ah/R0Bh[7:4], Table 12).
Interrupt signal for startup failures. TST_INT is the logic OR of the TSTART_ bits in the
Startup Event register (R08h/R09h[3:0], Table 11).
Interrupt signal for port overcurrent and current-limit violations. TCUT_INT is the logic OR
TCUT_INT
5
R
of the TCUT_ bits in the Fault Event register (R06h/R07h, Table 10) and the ICV_ bits in the
Startup Event register (R08h/R09h, Table 11).
CLS_INT
DET_INT
DIS_INT
PG_INT
PE_INT
4
3
2
1
0
R
R
R
R
R
Interrupt signal for completion of classification. CLS_INT is the logic OR of the CLS_ bits in
the Detect Event register (R04h/R05h, Table 9).
Interrupt signal for completion of detection. DET_INT is the logic OR of the DET_ bits in the
Detect Event register (R04h/R05h, Table 9).
Interrupt signal for a DC load disconnect. DIS_INT is the logic OR of the DIS_ bits in the
Fault Event register (R06h/R07h, Table 10).
Interrupt signal for PGOOD_ (R10h[7:4]) status changes. PG_INT is the logic OR of the
PG_CHG_ bits in the Power Event register (R02h/R03h, Table 8).
Interrupt signal for power enable status change. PE_INT is the logic OR of the PE_CHG_
bits in the Power Event register (R02h/R03h, Table 8).
30
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